1. Field of the Invention
The present invention relates to an access control method for multiprocessor systems, and more particularly to a method of controlling access to a bus or a memory, which dispenses with an exclusion control for the shared or common memory or the common bus and which can equalize the masterships of respective processors.
2. Description of the Prior Art
Heretofore, in a multiprocessor system including a plurality of processors, an error developing in the communication between the processors has posed problems. Moreover, since an exclusion control is performed in using a commom memory or a common bus, the bus becomes unusable for a long time, with the result that the inequality of masterships has arisen among the processors.
FIG. 1 is a block diagram of a prior-art multiprocessor system with a common memory.
In the multiprocessor system having the common memory, a plurality of processing modules (PM) 2, 3 which consist of processors 21, 31, local memories 22, 32 and interfaces 23, 33; the common memory (CM) 1; and a bus arbiter (BA) 4 are connected through a common bus 5. The respective processors 21, 31 can access the common memory 1 in quite the same manner that they access the local memories 22, 32.
FIG. 2 is a diagram showing a method for that communication between program modules which is executed in the system of FIG. 1. The program modules 24, 34 are stored in the local memories 22, 32 within the different processing modules 2, 3, and they are executed by the corresponding processors 21, 31. The communication between the program modules 24, 34 is performed through common data (CD) 11 which is stored in the common memory 1. Since the common data 11 is freely accessed from either desired program module at any desired time, the versatility of the communication between the processors is very high. On the other hand, however, when a bug exists in a program, it is difficult to detect the corresponding part so as to correct the bug.
The common memory 1 cannot be simultaneously accessed by two or more processors. The bus arbiter 4 performs an exclusion control for the common bus 5 so as to prevent the simultaneous access to the common memory by the plurality of processors. In addition, the processor 21 or 31 has the exclusion control function of excluding the opposite processor and completely occupying the common bus 5 while the common data 11 is accessed and updated. It is true that such exclusion control is indispensable to any common memory connection method. With the prior-art method, however, a common bus occupation time required for the exclusion control is too long. Therefore, when the number of the processors is large, the common bus inoccupation-waiting time of each processor becomes very large. This results in the disadvantage of incurring increase in the overhead of the whole system.
FIG. 3 is a diagram showing a bus control method in a prior-art multiprocessor system.
In the multiprocessor system wherein a plurality of processors 2, 3, . . . 6 are connected to an identical bus 5, the control is performed by the daisy chain method as illustrated in FIG. 3.
Now, when one of the processors 2, 3, . . . 6 has provided a request signal BR for the use of the bus, a bus arbiter 4 discriminates whether or not the bus is in the usable status, and it delivers a bus use grant signal BGOUT subject to the usable status. The bus use grant signal BGOUT is transmitted by the daisy chain in succession from the processor 2 which is physically closest to the bus arbiter 4, and it is received by the processor which has provided the bus use request signal BR. When, after one processor has acquired the bus mastership. the bus use request signal BR is provided from another processor, a bus busy signal BBSY is delivered from the occupying processor. The bus arbiter 4 receives these signals BR and BBSY, thereby to grasp the situation of the use of the bus.
FIG. 4 is a logical structure diagram of a bus control circuit for the processor in FIG. 3.
When the processor has issued a bus use request BR, a bus driver 15 is actuated to deliver the request signal BR. Also a flip-flop F2 is set in synchronism with the reception of a use grant signal BGIN, and a bus driver 16 is actuated by the resulting set output so as to deliver the bus busy signal BBSY. The bus use grant signal BGIN is delivered to the succeeding processor through an inverter 19, a delay line 18 and a NAND circuit 17. More specifically, after the flip-flop F2 has been reset by the inversion of the bus use request BR, occurring when the processor has stopped using the bus, or by a reset signal RESET, the NAND circuit 17 is enabled by the resulting reset output, whereby the use grant signal BGOUT is delivered to the adjoining processor.
Thus, each processor can freely provide the bus use request signal BR. Therefore, the processor physically closer to the bus arbiter 4 has a higher priority level for acquiring the mastership of the bus. In consequence, the processor located in a place physically remoter from the bus arbiter 4 has the bus use grant signal BGOUT blocked by the closer processor and cannot acquire the mastership. Accordingly, the bus masterships become very unequal.